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L6911E
5-Bit programmable step down controller with synchronous rectification
Features

Operating supply IC voltage from 5V to 12V buses Up to 1.3A gate current capability TTL-compatible 5 bit programmable output compliant with VRM 8.5 : 1.050V to 1.825V with 0.025V binary steps Voltage mode PWM control Excellent output accuracy: 1% over line and temperature variations Very fast load transient response: from 0% to 100% Duty Cycle Power good output voltage Overvoltage protection and monitor Overcurrent protection realized using the upper MOSFET's Rds(ON) 200kHz internal oscillator Oscillator externally adjustable from 50kHz to 1MHz Soft start and inhibit functions
SO-20

Description
The device is a power supply controller specifically designed to provide a high performance DC/DC conversion for high current microprocessors. A precise 5 bit digital to analog converter (DAC) allows to adjust the output voltage from 1.050 to 1.825 with 25mV binary steps. The high precision internal reference assures the selected output voltage to be within 1%. The high peak current gate drive affords to have fast switching to the external power mos providing low switching losses. The device assures a fast protection against load overcurrent and load over-voltage. An external SCR is triggered to crowbar the input supply in case of hard overvoltage. An internal crowbar is also provided turning on the low side mosfet as long as the over-voltage is detected. In case of over-current detection, the soft start capacitor is discharged an the system works in HICCUP mode.
Applications

Power supply for advanced microprocessor core Distributed power supply
Table 1. Device summary
Part Number L6911E L6911ETR April 2007 Package TSSOP8 TSSOP8 Rev 3 Packaging Tube Tape and reel 1/34
www.st.com 34
Contents
L6911E
Contents
1 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 3.2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 VID Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Digital to analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Soft start and inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Monitor and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Compensation network design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6
VRM demo board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1 6.2 6.3 6.4 6.5 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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L6911E
Contents
7 8 9 10
Connector pin orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PCB and components layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3/34
Block diagram
L6911E
1
Block diagram
Figure 1. Block diagram
Vcc 5V to12V Vin 5V to12V
PGOOD SS
VCC
OCSET BOOT
MONITOR and PROTECTION OVP RT
UGATE
OSC
PHASE LGATE PGND
Vo 1.050V to 1.825V
VD0 VD1 VD2 VD3 VD4 D/A + E/A + PWM
GND VSEN VFB
D98IN957
COMP
4/34
L6911E
Pin settings
2
2.1
Pin settings
Pin connection
Figure 2. Pin connection (top view)
VSEN OCSET SS/INH VID0 VID1 VID2 VID3 VID4 COMP FB 1 2 3 4 5 6 7 8 9 10
D98IN958
20 19 18 17 16 15 14 13 12 11
RT OVP VCC LGATE PGND BOOT UGATE PHASE PGOOD GND
2.2
Pin description
Table 2. Pin description
N 1 Name VSEN Description Connected to the output voltage is able to manage over-voltage conditions and the PGOOD signal. A resistor connected from this pin and the upper Mos Drain sets the current limit protection. The internal 200A current generator sinks a current from the drain through the external resistor. The Over-Current threshold is due to the following equation: I OCSET R OCSET I P = ----------------------------------------------R DSon The soft start time is programmed connecting an external capacitor from this pin and GND. The internal current generator forces through the capacitor 10A. This pin can be used to disable the device forcing a voltage lower than 0.4V Voltage Identification Code pins. These input are internally pulled-up and TTL compatible. They are used to program the output voltage as specified in Table 6 on page 9 and to set the overvoltage and power good thresholds. Connect to GND to program a `0' while leave floating to program a `1'. This pin is connected to the error amplifier output and is used to compensate the voltage control feedback loop. This pin is connected to the error amplifier inverting input and is used to compensate the voltage control feedback loop.
2
OCSET
3
SS/INH
4-8
VID0 - 4
9 10
COMP FB
5/34
Pin settings Table 2. Pin description (continued)
N 11 Name GND Description
L6911E
All the internal references are referred to this pin. Connect it to the PCB signal ground. This pin is an open collector output and is pulled low if the output voltage is not within the above specified threshlds. If not used may be left floating. This pin is connected to the source of the upper mosfet and provides the return path for the high side driver. This pin monitors the drop across the upper mosfet for the current limit. High side gate driver output. Bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper mosfet. Connect through a capacitor to the PHASE pin and through a diode to Vcc (catode vs boot). Power ground pin. This pin has to be connected closely to the low side mosfet source in order to reduce the noise injection into the device This pin is the lower mosfet gate driver output Device supply voltage. The operative supply voltage range is from 4.5 to 12V. DO NOT CONNECT VIN to 12V if VCC IS 5V. Over voltage protection. If the output voltage reach the 15% above the programmed voltage this pin is driven high and can be used to drive an external SCR that crowbar the supply voltage. If not used, it may be left floating. Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the external frequency is increased according to the equation: 5 10 f S = 200kHz + ------------------R T ( k )
6
12
PGOOD
13 14 15
PHASE UGATE BOOT
16 17 18
PGND LGATE VCC
19
OVP
20
RT
Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according to the equation: 4 10 f S = 200kHz - ------------------R T ( k ) If the pin is not connected, the switching frequency is 200KHz. The voltage at this pin is fixed at 1.23V. Forcing a 50A current into this pin, the built in oscillator stops to switch.
7
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L6911E
Electrical data
3
3.1
Electrical data
Maximum ratings
Table 3. Absolute maximum ratings
Symbol Vcc Vcc to GND, PGND Parameter (1) Value 15 15 15 OCSET, PHASE, LGATE ROSC, SS, FB, PGOOD, VSEN COMP, OVP -0.3 to Vcc+0.3 7 6.5 Unit V V V V V V
VBOOT-VPHASE Boot Voltage VHGATE-VPHASE
1. ESD immunity for pins 2 to 9 and 18 to 20 is guaranteed up to 1500V (Human Body Model).
3.2
Thermal data
Table 4. Thermal data
Symbol RthJA Tmax TSTG TJ Parameter Thermal resistance junction to ambient Maximum junction temperature Storage temperature range Junction temperature range Value 110 150 -40 to 150 0 to 125 Unit C/W C C C
7/34
Electrical characteristics
L6911E
4
Electrical characteristics
Table 5. Electrical characteristic (VCC = 12V; TA = 25C unless otherwise specified)
Symbol VCC supply current Icc Power-ON Turn-On VCC threshold Turn-Off VCC threshold Rising VOCSET threshold ISS Oscillator Free running frequency Total Variation VOSC Ramp amplitude RT = OPEN 6 K < RT to GND < 200 K RT = OPEN 180 -15 1.9 200 220 15 kHz % Vp-p Soft start current VOCSET = 4.5V VOCSET = 4.5V 3.6 1.26 10 4.6 V V V A Vcc supply current UGATE and LGATE open 5 mA Parameter Test condition Min Typ Max Unit
Reference and DAC DACOUT voltage accuracy VID0, VID1,VID2, VID3, VID25mV see Table 6 on page 9; TA = 0 to 70C -1 1 %
VID Pull-Up voltage Error amplifier DC gain GBWP SR Gain-bandwidth product Slew-rate COMP = 10pF
3.1
V
88 15 10
dB MHz V/S
Gate drivers IUGATE RUGATE ILGATE RLGATE High side source current VBOOT - VPHASE = 12V, VUGATE - VPHASE = 6V VBOOT - VPHASE = 12V, IUGATE = 300mA VCC = 12V, VLGATE = 6V Vcc=12V, ILGATE = 300mA PHASE connected to GND 0.9 1 1.3 A
High side sink resistance
2
4
Low side source current Low side sink resistance Output driver dead time
1.1 1.5 120 3
A nS
Protections Over voltage trip (VSEN/DACOUT) IOCSET 8/34 OCSET current source VSEN rising VOCSET = 4.5V 170 117 200 120 230 % A
L6911E
Electrical characteristics
Table 5. Electrical characteristic (VCC = 12V; TA = 25C unless otherwise specified) (continued)
Symbol IOVP Parameter OVP sourcing current Test condition VSEN > OVP trip, VOVP = 0V Min 60 Typ Max Unit mA
Power GOOD Upper threshold (VSEN/DACOUT) Lower threshold (VSEN/DACOUT) Hysteresis (VSEN/DACOUT) VPGOOD PGOOD voltage low VSEN rising VSEN falling Upper and lower threshold IPGOOD = -5mA 108 88 110 90 2 0.5 112 92 % % % V
4.1
VID Setting
Table 6. VID Setting
VID4 (25mV) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID3 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID2 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Output Voltage (V) 1.050 1.075 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 VID4 (25mV) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VID3 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 VID2 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Output Voltage (V) 1.450 1.475 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825
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Device description
L6911E
5
Device description
The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections for a high performance step-down DC-DC converter optimized for microprocessor power supply. It is designed to drive N Channel Mosfets in a synchronousrectified buck topology. The device works properly with Vcc ranging from 5V to 12V and regulates the output voltage starting from a 1.26V power stage supply voltage (Vin). The output voltage of the converter can be precisely regulated, programming the VID pins, from 1.050V to 1.825V with 25mV binary steps, with a maximum tolerance of 1% over temperature and line voltage variations. The device provides voltage-mode control with fast transient response. It includes a 200kHz free-running oscillator that is adjustable from 50kHz to 1MHz. The error amplifier features a 15MHz gain-bandwidth product and 10V/ms slew rate which permits high converter bandwidth for fast transient performance. The resulting PWM duty cycle ranges from 0% to 100%. The device protects against overcurrent conditions entering in HICCUP mode. The device monitors the current by using the rds(ON) of the upper MOSFET which eliminates the need for a current sensing resistor. The device is available in SO20 package.
5.1
Oscillator
The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the oscillator is tipically 50A (FSW = 200KHz) and may be varied using an external resistor (RT) connected between RT pin and GND or VCC. Since the RT pin is maintained at fixed voltage (typ. 1.235V), the frequency is varied proportionally to the current sinked (forced) from (into) the pin. In particular connecting it to GND the frequency is increased (current is sinked from the pin), according to the following relationship: Equation 1
4.94 10 f S = 200kHz + -----------------------R T ( k )
6
10/34
L6911E
Device description Connecting RT to VCC = 12V or to VCC = 5V the frequency is reduced (current is forced into the pin), according to the following relationships: Equation 2
4.306 10 f S = 200kHz + ---------------------------R T ( k )
7
VCC = 12V
Equation 3
15 10 f S = 200kHz + ------------------R T ( k )
7
VCC = 5V
Switching frequency variations vs. RT are reported in Figure 3 on page 11. Note: That forcing a 50A current into this pin, the device stops switching because no current is delivered to the oscillator. Figure 3. Switching frequency variations vs. RT
10000
1000
Resistance [kOhm]
100
10
RT to GND RT to VCC=12V RT to VCC=5V
10
100
1000
Frequency [kHz]
11/34
Device description
L6911E
5.2
Digital to analog converter
The built-in digital to analog converter allows the adjustment of the output voltage from 1.050V to 1.825V with 25mV binary steps as shown in the previous Table 6: VID Setting on page 9. The internal reference is trimmed to ensure the precision of 1%. The internal reference voltage for the regulation is programmed by the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is realised by means of a series of resistors rpoviding a partition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier obtaining the VPROG voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are provided (realized with a 5A current generator); in this way, to program a logic "1" it is enough to leave the pin floating, while to program a logic "0" it is enough to short the pin to GND. The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the over- voltage protection (OVP) thresholds.
5.3
Soft start and inhibit
At start-up a ramp is generated charging the external capacitor CSS by means of a 10A constant current, as shown in Figure 4 on page 13 When the voltage across the soft start capacitor (VSS) reaches 0.5V the lower power MOS is turned on to discharge the output capacitor. As VSS reaches 1V (i.e. the oscillator triangular wave inferior limit) also the upper MOS begins to switch and the output voltage starts to increase. The VSS growing voltage initially clamps the output of the error amplifier, and consequently VOUT linearly increases, as shown in Figure 4 on page 13. In this phase the system works in open loop. When VSS is equal to VCOMP the clamp on the output of the error amplifier is released. In any case another clamp on the non-inverting input of the error amplifier remains active, allowing to VOUT to grow with a lower slope (i.e. the slope of the VSS voltage, see Figure 4 on page 13). In this second phase the system works in closed loop with a growing reference. As the output voltage reaches the desired value VPROG, also the clamp on the error amplifier input is removed, and the soft start finishes. Vss increases until a maximum value of about 4V. The Soft-Start will not take place, and the relative pin is internally shorted to GND, if both VCC and OCSET pins are not above their own Turn-On thresholds; in this way the device starts switching only if both the power supplies are present. During normal operation, if any under-voltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly discharged. The device goes in INHIBIT state forcing SS pin below 0.4V. In this condition both external MOSFETS are kept OFF.
12/34
L6911E Figure 4. Soft start
Vcc Turn-on threshold
Device description
Vcc Vin
Vin Turn-on threshold Vss
to GND
1V 0.5V
LGATE
Vout
Timing diagram
Aquisition: CH1 = PHASE; CH2 = VOUT; CH3 = PGOOD; CH4 = VSS CH3 = PGOOD; CH4 = VSS
5.4
Driver section
The driver capability on the high and low side drivers allows to use different types of power MOS (also multiple MOS to reduce the Rds(ON)), maintaining fast switching transition. The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin. Adaptative dead time control is implemented to prevent cross-conduction and allow to use many kinds of mosfets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is avoided if the PHASE pin is over about 500mV. The upper mos is in any case turned-on after 200nS from the low side turn-off. The peak current is shown for both the upper (Figure 5 on page 14) and the lowr (Figure 6 on page 14) driver at 5V and 12V. a 4nF capacitive load has been used in these measurements. For the lower driver, the source peak current is 1.1A @ VCC = 12V and 500mA @ VCC = 5V, and the sink peak current is 1.3A @ VCC = 12V and 500mA @ VCC = 5V. Similary, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase = 12V and 600mA @ Vboot-Vphase = 5V, and the sink peak current is 1.3A @ Vboot-Vphase = 12V and 550mA @ Vboot-Vphase = 5V.
13/34
Device description Figure 5.
L6911E High side driver peak current, Vboot-Vphase=12V (left) Vboot-Vphase=5V (right) CH1 = High Side Gate CH4 = inductor current
Figure 6.
Low side driver peak current, VCC=12V (left) VCC=5V (right)CH1 = Low side gate CH4 = inductor current
14/34
L6911E
Device description
5.5
Monitor and protection
The output voltage is monitored by means of pin 1 (VSEN). If it is not within 10% (typ.) of the programmed value, the powergood output is forced low. The device provides overvoltage protection, when the output voltage reaches a value 17% (typ.) greater than the nominal one. If the output voltage exceed this threshold, the OVP pin is forced high (5V) and the lower driver is turned on as long as the over-voltage is detected. The OVP pin is capable to deliver up to 60mA (min) in order to trigger an external SCR connected to burn the input fuse. The low-side mosfet turn-on implement this function when the SCR is not used and helps in keeping the ouput low. To perform the overcurrent protection the device compares the drop across the high side MOS, due to its RDSON, with the voltage across the external resistor (ROCS) connected between the OCSET pin and drain of the upper MOS. Thus the overcurrent threshold (IP) can be calculated with the following relationship: Equation 4
I OCS R OCS I P = ------------------------------R DSON
where the typical value of IOCS is 200A. To calculate the ROCS value it must be considered the maximum RDSON (also the variation with temperature) and the minimum value of IOCS. To avoid undesirable trigger of overcurrent protection this relationship must be satisfied: Equation 5
l I P I OUTMAX + ---- = I PEAK 2
where I is the inductance ripple current and IOUTMAX is the maximum output current. In case of output short circuit the soft start capacitor is discharged with constant current (10A typ.) and when the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is always active and if such kind of event occours, the device turns off both mosfets, and the SS capacitor is dicharged again after reaching the upper threshold of about 4V. The system is now working in HICCUP mode, as shown in Figure 7 on page 16 a. After removing the cause of the over-current, the device restart working normally without power supplies turn off and on.
15/34
Device description Figure 7. Hiccup mode and Inductor ripple current vs. VOUT
9 8
L=1.5H, Vin=12V
L6911E
Inductor Ripple [A]
7 6 5 4 3 2 1 0 0.5 1.5 2.5
L=2H, Vin=12V L=3H, Vin=12V L=1.5H, Vin=5V L=2H, Vin=5V L=3H, Vin=5V
3.5
Output V oltage [V ]
a) b)
5.6
Inductor design
The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current IL between 20% and 30% of the maximum output current. The inductance value can be calculated with this relationship: Equation 6
V IN - V OUT V OUT L = ----------------------------- -------------f s I L V IN
Where fSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Figure 7 b shows the ripple current vs. the output voltage for different values of the inductor, with vin = 5V and Vin = 12V. Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter response time to a load transient. If the compensation network is well designed, the device is able to open or close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to change its current from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance required. The response time to a load transient is different for the application or the removal of the load: if during the application of the load the inductor is charged by a voltage equal to the difference between the input and the output voltage, during the removal it is discharged only by the output voltage. The following expressions give approximate response time for I load transient in case of enough fast compensation network response:
16/34
L6911E Equation 7
L I t application = ----------------------------V IN - V OUT
Device description
Equation 8
L I t removal = -------------V OUT
The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst case is the response time after removal of the load with the minimum output voltage programmed and the maximum input voltage available.
5.7
Output capacitor
Since the microprocessors require a current variation beyond 10A doing load transients, with a slope in the range of tenth A/sec, the output capacitor is a basic component for the fast response of the power supply. In fact for first few microseconds they supply the current to the load. The controller recognizes immediately the load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL): Equation 9
VOUT = IOUT * ESR
A minimum capacitor value is required to sustain the current during the load transient without discharge it. The voltage drop due to the output capacitor discharge is given by the following equation: Equation 10
I OUT L V OUT = ------------------------------------------------------------------------------------------2 C OUT ( V INMIN D MAX - V OUT )
2
Where DMAX is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop during load transient and the lower is the output voltage static ripple.
17/34
Device description
L6911E
5.8
Input capacitor
The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must have a low ESR to minimize the losses. The rms value of this ripple is: Equation 11
I rms = I OUT D ( 1 - D )
Where D is the duty cycle. The equation reaches its maximum value with D = 0.5. The losses in worst case are: Equation 12
P = ESR I rms
2
5.9
Compensation network design
The control loop is a voltage mode (Figure 9 on page 19) that uses a droop function to satisfy the requirements for a VRM module, reducing the size and the cost of the output capacitor. This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a dependence of the output voltage on the load current: at light load the output voltage will be higher than the nominal level, while at high load the output voltage will be lower than the nominal value. Figure 8. Output transient response without (a) and with (b) the droop function
18/34
L6911E
Device description As shown in Figure 8 on page 18, the ESR drop is present in any case, but using the droop function the total deviation of the output voltage is minimized. In practice the droop function introduces a static error (Vdroop in Figure 8 on page 18) proportional to the output current. Since a sense resistor is not present, the output DC current is measured by using the intrinsic resistance of the inductance (a few m). So the low-pass filtered inductor voltage (that is the inductor current) is added to the feedback signal, implementing the droop function in a simple way. Referring to the schematic in Figure 9, the static characteristic of the closed loop system is: Equation 13
R3 + R8 // R9 R L R8 // R9 V OUT = V PROG + V PROG ------------------------------------ - --------------------------------- I OUT R8 R2
Where VPROG is the output voltage of the digital to analog converter (i.e. the set point) and RL is the inductance resistance. The second term of the equation allows a positive offset at zero load (V+); the third term introduces the droop effect (VDROOP). Note that the droop effect is equal the ESR drop if: Equation 14
R L R8 // R9 --------------------------------- = ESR R8
Figure 9.
Compensation network
V
IN
V
COMP
V
PHASE
L2
R
L
V
OUT
PW M
R8 C18 ESR
ZF
C 20 R4 R9
C 6 -1 5
R3
C 25
V
PROG
ZI
R2
19/34
Device description
L6911E
Considering the previous relationships R2, R3, R8 and R9 may be determined in order to obtain the desired droop effect as follow:

Choose a value for R2 in the range of hundreds of K to obtain realistic values for the other components. From the above equations, it results:
Equation 15
+ V R2 R L I MAXR8 = ---------------------- ------------------------V PROG V DROOP
Equation 16
V DROOP 1 R9 = R8 ------------------------- ----------------------------------R L I MAX V DROOP 1 + ------------------------R L I MAX
Where IMAX is the maximum output current.
The component R3 must be chosen in order to obtain R3 << R8//R9 to permit these and successive simplifications.
Therefore, with the droop function the output voltage decreases as the load current increases, so the DC output impedance is equal to a resistance ROUT. It is easy to verify that the output voltage deviation under load transient is minimum when the output impedance is constant with frequency.
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L6911E
Device description To choose the other components of the compensation network, the transfer function of the voltage loop is considered. To simplify the analysis is supposed that R3 << Rd, where Rd = (R8//R9). Figure 10. Compensation network definition
|A v |
2
fLC |R |
fC E
fE C
fC C
f
R0
fD |G lo o p | G0
f2
f1
f3
f
fc f
ConverterS ingularity
fLC = 1 / 2
LC
doublepole ESRzero Introduced by CeramicCap acitor
Compensati onNetworkS ingularity
fCE = 1 / 2 ESR C OUT = 1 / 2 ESR Cceramic f EC = 1 / 2 Rceramic Cceramic f CC
f1 = 1 / 2 R 4 C 20 f 2 = 1 / 2 ( R 3 + R 4 ) C 20 f3 = 1 / 2 R 3 C 25 fd = 1 / 2 Rd C 25
The transfer function may be evaluated neglecting the connection of R8 to PHASE because, as will see later, this connection is important only at low frequencies. So R4 is considered connected to VOUT. Under this assumption, the voltage loop has the following transfer function: Equation 17
Zf ( s ) Gloop ( s ) = Av ( s ) R ( s ) = Av ( s ) ------------Zi ( s ) ZC ( s ) Vin Av ( s ) = --------------- ----------------------------------V osc Z C ( s ) + Z L ( s )
where
Where ZC(s) and ZL(s) are the output capacitor and inductor impedance respectively. The expression of ZI(s) may be simplified as follow:
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Device description Equation 18
L6911E
2 R3 1 1 + s R3 ( 1 1 ------- d Rd 1 + s ( 1 + d ) + s ------- 1 d Rd -- C25 R4 + -- C20 R3 Rd Rd s s ------------------------------------------------------------------------------------------------- = Rd ------------------------------------------------------------------------------ + ---------------------------------------------------- = ( 1 + s 2 ) ( 1 + s d ) ( 1 + s 2 ) ( 1 + Rd + 1 C25 R4 + 1 C20 + R3 --s s
Where: 1 = R4 x C20, 2 = (R4+R3) x C20 and d = Rd x C25. The regulator transfer function became now: Equation 19
( 1 + s 2 ) ( 1 + s d ) R ( s ) ------------------------------------------------------------------------------------------------------R3 s C18 R d 1 + s ------- d ( 1 + s 1 ) Rd
Figure 10 on page 21 shows a method to select the regulator components (please note that the frequencies fEC and fCC corresponds to the singularities introduced by additional ceramic capacitors in parallel to the output main electrolytic capacitor).
To obtain a flat frequency response of the output impedance, the droop time constant d has to be equal to the inductor time constant (see the note at the end of the section):
Equation 20
L d = R d C25 = ------ = L RL
L C25 = ---------------------( RL Rd )
To obtain a constant -20dB/dec Gloop(s) shape the singularity f1 and f2 are placed in proximity of fCE and fLC respectively. This implies that:
Equation 21
f LC f2 --- = ------f CE f1 f1 = f CE

f LC R4 = R3 ------- - 1 f
CE
1 C20 = -- R4 f CE 2
To obtain a Gloop bandwidth of fC, results:
Equation 22
f LC = 1 f C
fC VIN - C20 // C25 G 0 = A 0 R 0 = ----------------- ---------------------------- = ------f LC Vosc C18
VIN - C20 C25 C18 = ----------------- ---------------------------Vosc C20 + C25
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L6911E Note:
Device description To understand the reason of the previous assumption, the scheme in Figure 11 on page 23 must be considered.
In this scheme, the inductor current has been substituted by the load current, because in the frequencies range of interest for the Droop function these current are substantially the same and it was supposed that the droop network don't represent a charge for the inductor. Figure 11. Voltage regulation with droop function block scheme
V com p
A v(s)
V ou t
R (s)
R OUT
1+ s L 1+ s d
Io ut
It results: Equation 23
G LOOP 1 + s L 1 + s L Vo Z OUT = -------------- = R d ----------------- --------------------------- = R OUT ----------------1 + s d 1 + G LOOP 1 + s d I LOAD
Because in the interested range |Gloop|>>1. To obtain a flat shape, the relationship considered will naturally follow.
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VRM demo board description
L6911E
6
VRM demo board description
Figure 12 shows the schematic circuit of the VRM evaluation board. The design has been developed for a VRM 8.5 Flexible Motherboard applicaton delivering up to 28.5A. An additional circuit sense a Vtt bus (1.2V typ.) and generate a 2.5mS (typ.) delayed Vtt_PWRGD signal when this rail is over 1.1V. The assertion of the Vtt_PWRGD signal enables the device together with the ENOUT input.
Figure 12. Schematic circuit
L1
+5 VIN
F1
OVP
BOOT
D1 +12Vcc R14 C12 VID0 VID1 VID2 VID3 VID25mV R1
VCC GND VID0 VID1 VID2 VID3 VID4 OSC SS
C11 2 14 13
OCSET
C10 R7
C1-3
15 18 11 4 5 6 7 8 20 3 9
COMP
19
UGATE
PHASE
Q1,Q2
L2 VOUTCORE
U1 17 L6911E
16 12 1 10
VFB
LGATE
PGND
Q3,Q4,Q5
D2
C4-9
R15
R6
Vss
PGOOD
PWRGD
VSEN
C13 Q7
R8 R3 C20 R4 R9 C17
C18 C19
R5
C14
RESET Vdd NOT RESIN GND 8 2 6 5 NOT RESET
R2
UZ TLC7701 4
7 3 1 CONTROL
D3
CT
Vtt_PGOOD
Vtt_sense C16
SENSE
C15
R13
OUTEN
R10
Q6 R11
R12
L6911E CONNECTOR EVALUATION KIT REV. 1.1
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L6911E
VRM demo board description
6.1
Efficiency
The measured efficiency versus load current at different output voltages is shown in Figure 13. In the application two Mosfets STS12NF30L (30V, 8.5m typ with VGS = 12V) connected in parallel are used for the High Side, while three of them are used for the Low Side. Figure 13. Efficiency vs. load current
Efficiency [%]
90 80 70 60 50 40 0 5 10
Vout = 1.825V Vout = 1.225V Vout = 1.500V
Output Current [A]
15
20
25
6.2
Inductor design
Since the maximum output current is 28.5A, to have a 20% ripple (5A) the inductor chosen is 1.5H.
6.3
Output capacitor
In the demo six OSCON capacitors, model 6SP680M, are used, with a maximum ESR equal to 12m each. Therefore the resultant ESR is of 2m. For load transient of 28.5A in the worst case the voltage drop is of: Equation 24 Vout = 28.5 * 0.002 = 57mV
The voltage drop due to the capacitor discharge during load transient, considering that the maximum duty cicle is equal to 100% results in 46.5mV with 1.85V of programmed output.
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VRM demo board description
L6911E
6.4
Input capacitor
For IOUT = 28.5A and with D = 0.5(worst case for input current ripple), Irms is equal to 17.8A. Three OSCON electrolityc capacitors 6SP680M, with a maximum ESR equal to 12m, are chosen to substain the ripple. So the losses in worst case are: Equation 25
P = ESR I rms = ( 1.25 ( 670 )m )W
2
6.5
Over-current protection
Substituting the demo board parameters in the relationship reported in the relative section, (IOCSMIN = 170A; IP =33A; RDSONMAX = 3m) it results that ROCS = 1k.
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L6911E
Connector pin orientation
7
Connector pin orientation
Table 7. Connector pin orientation
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Mechanical Key 18 19 20 21 22 23 24 25 Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE 33 32 31 30 29 28 27 26 Vss VccCORE Vss VccCORE Vss VccCORE Vss VccCORE Row A 5Vin 5Vin 5Vin 5Vin 12Vin 12Vin Reserved VID0 VID2 VID4 (25mV) OUTEN VTT_PWRGD Vss VccCORE VccCORE Vss VccCORE Pin # 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 Row B 5Vin 5Vin 5Vin 5Vin 12Vin 12Vin No Contact VID1 VID3 PWRGD Ishare VTT Vss Vss VccCORE Vss VccCORE
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PCB and components layout
L6911E
8
PCB and components layout
Figure 14. PCB and components layouts
Component side silkscreen
Component side
Figure 15. PCB and components layouts
Internal Layer
Internal Ground Plane
Figure 16. PCB and components layouts
Solder Side
Solder Side Silkscreen
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L6911E
PCB and components layout
Table 8. Part list
Resistors R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 Not Mounted 470K 1K 82 Not Mounted 20K 680 13K 100K 6.8K 10K 1K 10K 8.2 1K Capacitors C1-C3 C4-C9 C10 C11,C13-C16 C12 C17 C18 C19 C20 680F- 6.3V 820 F - 4V or 680F - 6.3V 1nF 100nF 1F 47nF 3.3nF Not Mounted 100nF Magnetics L1 L2 1.5H 1.8H T44-52 Core, 7T - 18AWG T50-52B Core, 8T - 16AWG Transistors Q1-Q5 Q6 Q7 STS12NF30L or FDS6670 Signal NPN BJT Signal MOSFET STMicroelectronics Fairchild SO8 SO8 SOT23 SOT23 OSCON 6SP680M OSCON 4SP820M OSCON 6SP680M Radial 10x10.5 Radial 10x10.5 Radial 10x10.5 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 1% 1% 1% SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805 SMD 0805
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PCB and components layout Table 8. Part list (continued)
Diodes D1 D2 D3 Ics U1 U2 L6911E TLC7701QD Fuse F1 251015A-15A Littlefuse STMicroelectronics Texas Instruments 1N4148 STPS3L25U STMicroelectronics
L6911E
SOT23 SMB
SO20 SO8
AXIAL
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L6911E
Package mechanical data
9
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
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Package mechanical data Figure 17. SO20 Mechanical data & package dimensions
mm DIM. MIN. A A1 B C D (1) E e H h L k ddd 10.0 0.25 0.40 2.35 0.10 0.33 0.23 12.60 7.40 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.30 0.51 0.32 13.00 7.60 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 TYP. MAX. 0.104 0.012 0.200 0.013 0.512 0.299 inch
L6911E
OUTLINE AND MECHANICAL DATA
0 (min.), 8 (max.) 0.10 0.004
(1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side.
SO20
0016022 D
32/34
L6911E
Revision history
10
Revision history
Table 9. Revision history
Date 15-Nov-2001 10-Apr-2007 Revision 2 3 Preliminary version Document has been reformatted, updated Table 3. Changes
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L6911E
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